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Anna Wong Phones & Addresses

  • 2025 California St, Mountain View, CA 94040
  • Lancaster, CA
  • 280 Howland St, Redwood City, CA 94063
  • Santa Clara, CA
  • San Francisco, CA
  • Elk Grove, CA

Professional Records

Real Estate Brokers

Anna Wong Photo 1

Anna Wong, San Mateo CA Realtor

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Specialties:
Buyer's Agent
Listing Agent
Work:
Alain Pinel Realtors
520 S. El Camino Real, Suite 100, San Mateo, CA 94402
(650) 548-1111 (Office)

Medicine Doctors

Anna Wong Photo 2

Dr. Anna Wong, Oakland CA - PHD

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Specialties:
Clinical Psychology
Address:
3505 Broadway, Oakland, CA 94611
(510) 752-1471 (Phone), (510) 752-1404 (Fax)
Languages:
English
Anna Wong Photo 3

Anna Wong

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Specialties:
Neurology
Work:
Swedish Medical GroupSwedish Neuroscience Institute Specialists Epilepsy Center
550 17 Ave STE 540, Seattle, WA 98122
(206) 320-3492 (phone), (206) 320-3088 (fax)

Swedish Hospital Neurology Science Institute
550 17 Ave STE 400, Seattle, WA 98122
(206) 320-3494 (phone), (206) 386-2845 (fax)
Education:
Medical School
Mem Univ of Newfoundland, Fac of Med, St Johns, Nfld, Canada
Graduated: 1994
Languages:
English
Description:
Dr. Wong graduated from the Mem Univ of Newfoundland, Fac of Med, St Johns, Nfld, Canada in 1994. She works in Seattle, WA and 1 other location and specializes in Neurology. Dr. Wong is affiliated with Swedish Medical Center - First Hill.
Anna Wong Photo 4

Anna Wong

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Specialties:
Family Medicine
Work:
New York Methodist Associates Of Bensonhurst
7400 18 Ave, Brooklyn, NY 11204
(718) 236-9446 (phone), (718) 236-3854 (fax)
Languages:
Arabic
Chinese
English
Italian
Spanish
Description:
Ms. Wong works in Brooklyn, NY and specializes in Family Medicine. Ms. Wong is affiliated with New York Methodist Hospital.

License Records

Anna Wong

License #:
1233 - Expired
Category:
Individual Optometrist
Issued Date:
Aug 20, 2002
Expiration Date:
Mar 8, 2003
Type:
Pharmaceutical Agent (orals)

Lawyers & Attorneys

Anna Wong Photo 5

Anna May Wong - Lawyer

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Address:
Herbert Smith Freehills LLP
(495) 363-6500 (Office)
Licenses:
New York - Currently registered 2011
Education:
New York University School of Law

Resumes

Resumes

Anna Wong Photo 6

Anna Wong Walnut Creek, CA

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Work:
Phi Beta Lambda Business Club
Concord, CA
Sep 2009 to Dec 2009
Member

John Muir Health
Walnut Creek, CA
Jun 2008 to Aug 2008
Summer Youth Program Intern

Longs (CVS)
Walnut Creek, CA
Apr 2008 to Jun 2008
Cashier

Panda Express
Walnut Creek, CA
Dec 2007 to Apr 2008
Cashier

Animal Rescue Foundation
Walnut Creek, CA
Sep 2005 to Feb 2006
Volunteer

Education:
University of California
Davis, CA
Aug 2012
Bachelor of Arts in Economics

Anna Wong Photo 7

Anna Wong San Jose, CA

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Work:
Hantronix, Inc
Cupertino, CA
Jul 1997 to Apr 2013
Buyer

Cupertino Chamber of Commerce
Cupertino, CA
Jan 1996 to May 1996
Administrative Coordinator

Education:
San Jose State University
San Jose, CA
May 1997
BA in Social Science

Skills:
Proficient in MS Word, MS Excel, Accpac ERP system General knowledge of Accounting principles, A/R, A/P Familiarity with overseas shipping and transport logistics

Business Records

Name / Title
Company / Classification
Phones & Addresses
Anna Wong
Assistant to Eve
Airtrade International Travel Canada Inc
Airtrade International Canada Inc.. Budgetair.ca
Online Travel Agency
200 4170 Still Creek Dr, Burnaby, BC V5C 6C6
(778) 836-6015
Anna Wong
Assistant to Eve
Airtrade International Travel Canada Inc
Airtrade International Canada Inc.. Budgetair.ca
Online Travel Agency
200 4170 Still Creek Dr, Burnaby, BC V5C 6C6
(778) 836-6015
Anna Wong
Managing
Rose Walk, LLC
Investment · Real Estate Investments
254 Bayview Ave, Tiburon, CA 94920
1 Blackfield Dr, Tiburon, CA 94920
Anna Wong
Assistant to Eve
Airtrade International Travel Canada Inc
Online Travel Agency
(778) 836-6015
Anna C. Wong
Strategic Business Advisers LLC
20230 Arthur Ct, Santa Clarita, CA 91350
Anna Wong
1081 Leconte, LLC
Property Investment · Business Services at Non-Commercial Site
79 Madrone Ave, San Francisco, CA 94127
Anna Wong
GARDEN CAFE' LLC
Anna M. Wong
President
Amw Firearms Inc
Ret Sporting Goods/Bicycles
40611 Grimmer Blvd, Fremont, CA 94538
3246 Santa Isabella Ct, Union City, CA 94587
Anna Wong
Managing
Island Living LLC
Real Property Ownership Investment and R
254 Bayview Ave, Tiburon, CA 94920

Publications

Us Patents

Digital Signal Processing Circuit Having A Pattern Detector Circuit

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US Patent:
20060195496, Aug 31, 2006
Filed:
May 12, 2006
Appl. No.:
11/432846
Inventors:
Vasisht Vadi - San Jose CA,
Jennifer Wong - Fremont CA,
Bernard New - Carmel Valley CA,
Alvin Ching - Sunnyvale CA,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
James Simkins - Park City UT,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 15/00
US Classification:
708200000
Abstract:
An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Digital Signal Processing Block Having A Wide Multiplexer

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US Patent:
20060212499, Sep 21, 2006
Filed:
May 12, 2006
Appl. No.:
11/433120
Inventors:
Bernard New - Carmel Valley CA,
Vasisht Vadi - San Jose CA,
Jennifer Wong - Fremont CA,
Alvin Ching - Sunnyvale CA,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
James Simkins - Park City UT,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 15/00
US Classification:
708200000
Abstract:
A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Architectural Floorplan For A Digital Signal Processing Circuit

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US Patent:
20060230092, Oct 12, 2006
Filed:
May 12, 2006
Appl. No.:
11/433369
Inventors:
Alvin Ching - Sunnyvale CA,
Jennifer Wong - Fremont CA,
Bernard New - Carmel Valley CA,
James Simkins - Park City UT,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
Vasisht Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708490000
Abstract:
A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Digital Signal Processing Circuit Having A Pattern Detector Circuit For Convergent Rounding

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US Patent:
20060230093, Oct 12, 2006
Filed:
May 12, 2006
Appl. No.:
11/432847
Inventors:
Bernard New - Carmel Valley CA,
Jennifer Wong - Fremont CA,
James Simkins - Park City UT,
Alvin Ching - Sunnyvale CA,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
Vasisht Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708551000
Abstract:
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Digital Signal Processing Circuit Having Input Register Blocks

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US Patent:
20060230094, Oct 12, 2006
Filed:
May 12, 2006
Appl. No.:
11/432823
Inventors:
James Simkins - Park City UT,
Jennifer Wong - Fremont CA,
Bernard New - Carmel Valley CA,
Alvin Ching - Sunnyvale CA,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
Vasisht Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/52
US Classification:
708625000
Abstract:
An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Digital Signal Processing Circuit Having A Pre-Adder Circuit

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US Patent:
20060230095, Oct 12, 2006
Filed:
May 12, 2006
Appl. No.:
11/432848
Inventors:
James Simkins - Park City UT,
John Thendean - Berkeley CA,
Vasisht Vadi - San Jose CA,
Bernard New - Carmel Valley CA,
Jennifer Wong - Fremont CA,
Anna Wong - Santa Clara CA,
Alvin Ching - Sunnyvale CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/50
US Classification:
708700000
Abstract:
A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Digital Signal Processing Circuit Having An Adder Circuit With Carry-Outs

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US Patent:
20060230096, Oct 12, 2006
Filed:
May 12, 2006
Appl. No.:
11/433517
Inventors:
John Thendean - ,
Jennifer Wong - Fremont CA,
Bernard New - Carmel Valley CA,
Alvin Ching - Sunnyvale CA,
James Simkins - Park City UT,
Anna Wong - Santa Clara CA,
Vasisht Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/50
US Classification:
708700000
Abstract:
An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Digital Signal Processing Circuit Having A Simd Circuit

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US Patent:
20060288069, Dec 21, 2006
Filed:
May 12, 2006
Appl. No.:
11/433331
Inventors:
James Simkins - Park City UT,
Jennifer Wong - Fremont CA,
Bernard New - Carmel Valley CA,
Alvin Ching - Sunnyvale CA,
John Thendean - Berkeley CA,
Anna Wong - Santa Clara CA,
Vasisht Vadi - San Jose CA,
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 7/38
US Classification:
708524000
Abstract:
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
Anna Wong from Mountain View, CA, age ~67 Get Report