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Hari Mony Phones & Addresses

  • Cedar Park, TX
  • 16516 Castletroy Dr, Austin, TX 78717
  • 2600 Scofield Ridge Pkwy, Austin, TX 78727
  • 2601 Scofield Ridge Pkwy, Austin, TX 78727
  • 11900 Hobby Horse Ct, Austin, TX 78758
  • 3815 Guadalupe St, Austin, TX 78751
  • 301 29Th St, Austin, TX 78705

Resumes

Resumes

Hari Mony Photo 1

Hari Mony

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Location:
Austin, Texas Area
Industry:
Computer Hardware
Hari Mony Photo 2

Hari Mony

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Location:
Austin und Umgebung, Texas
Industry:
Computer-Hardware

Publications

Us Patents

Use Of Time Step Information In A Design Verification System

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US Patent:
6993734, Jan 31, 2006
Filed:
Feb 20, 2003
Appl. No.:
10/371002
Inventors:
Jason Raymond Baumgartner - Austin TX,
Hari Mony - Austin TX,
Viresh Paruthi - Austin TX,
Mark Allen Williams - Plesant Valley NY,
Assignee:
International Business Machines Corporatioin - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 4, 716 6, 703 13, 703 19
Abstract:
The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a property during N time steps of its operation. The value of N is recorded and propagated. The propagated value of N is used to reduce resources expended during subsequent analysis of the integrated circuit by ignoring the model's adherence to the property during the early stages of subsequent analysis (during time steps less than N). The system may include a diameter estimator that identifies a value of N beyond which subsequent modeling of the integrated circuit produces no new states. Property checking is ignored during states having a time step value greater than the estimated diameter.

Predicate-Based Compositional Minimization In A Verification Environment

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US Patent:
8086429, Dec 27, 2011
Filed:
Jul 7, 2008
Appl. No.:
12/168469
Inventors:
Jason R. Baumgartner - Austin TX,
Hari Mony - Austin TX,
Viresh Paruthi - Austin TX,
Fadi A. Zaraket - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 7/44
US Classification:
703 2, 703 14, 703 22, 703 24, 716 2, 716 8, 716 9
Abstract:
A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.

Optimal Correlated Array Abstraction

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US Patent:
8245166, Aug 14, 2012
Filed:
Aug 31, 2010
Appl. No.:
12/871962
Inventors:
Jason R. Baumgartner - Austin TX,
Michael L. Case - Pflugerville TX,
Robert L. Kanzelman - Rochester MN,
Hari Mony - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716111
Abstract:
Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist. In addition, the mechanisms utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.

Method For Scalable Derivation Of An Implication-Based Reachable State Set Overapproximation

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US Patent:
8201117, Jun 12, 2012
Filed:
Jan 22, 2009
Appl. No.:
12/357907
Inventors:
Jason R. Baumgartner - Austin TX,
Michael L. Case - Pflugerville TX,
Geert Janssen - Putnam County NY,
Hari Mony - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716107
Abstract:
A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction.

Scalable Reduction In Registers With Sat-Based Resubstitution

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US Patent:
8201115, Jun 12, 2012
Filed:
Aug 14, 2008
Appl. No.:
12/191635
Inventors:
Jason R. Baumgartner - Austin TX,
Michael L. Case - Pflugerville TX,
Hari Mony - Austin TX,
Viresh Paruthi - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716106, 716103, 716107, 716110, 716111, 716112, 716136, 703 13, 703 14
Abstract:
A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.

Performing Minimization Of Input Count During Structural Netlist Overapproximation

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US Patent:
8185852, May 22, 2012
Filed:
Mar 13, 2008
Appl. No.:
12/047361
Inventors:
Jason R. Baumgartner - Austin TX,
Robert L. Kanzelman - Rochester MN,
Hari Mony - Austin TX,
Viresh Paruthi - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716106, 716107
Abstract:
A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut.

Techniques For Performing Conditional Sequential Equivalence Checking Of An Integrated Circuit Logic Design

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US Patent:
8181134, May 15, 2012
Filed:
Oct 16, 2009
Appl. No.:
12/580373
Inventors:
Jason R. Baumgartner - Austin TX,
Michael L. Case - Pflugerville TX,
Hari Mony - Austin TX,
Jun Sawada - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716107, 716103, 716104, 716111, 703 16
Abstract:
A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded.

Enhanced Analysis Of Array-Based Netlists Via Reparameterization

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US Patent:
8181131, May 15, 2012
Filed:
Apr 30, 2010
Appl. No.:
12/771613
Inventors:
Jason R. Baumgartner - Austin TX,
Michael L. Case - Pflugerville TX,
Robert L. Kanzelman - Rochester MN,
Hari Mony - Austin TX,
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
G06F 17/50
G06F 9/45
US Classification:
716103, 716106, 716111
Abstract:
A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition which enables optimal reductions though input reparameterization given a netlist with constraints. A post-processing mechanism next prevents input reparameterization from creating topologically inconsistent models in the presence of arrays. Additionally, this technique may be used to rectify inconsistent topologies that may arise when reparameterizing even netlists without arrays, namely false sequential dependencies across initialization constructs. Furthermore, a mechanism is provided to undo the effects of memory array based input reparameterization on verification results.
Hari Mony from Cedar Park, TX, age ~43 Get Report