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Hari Mony

from Cedar Park, TX
Age ~46
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Related to:
Suchitra MonySuchitra Iyer, 41
Connected to:
Keo Mony, 58Justin A Monych, 26Shelley Monych, 60Pete A Monyer, 79Stephen B Monyer, 50Eileen C Monyok, 63Jason E Monz, 46Audrey K Monzeglio, 58Steven Monzillo, 57Denis A Monzin, 43

Hari Mony Phones & Addresses

  • Cedar Park, TX
  • 16516 Castletroy Dr, Austin, TX 78717
  • 2600 Scofield Ridge Pkwy, Austin, TX 78727
  • 2601 Scofield Ridge Pkwy, Austin, TX 78727
  • 11900 Hobby Horse Ct, Austin, TX 78758
  • 3815 Guadalupe St, Austin, TX 78751
  • 301 29Th St, Austin, TX 78705

Resumes

Resumes

Hari Mony Photo 1

Principal Architect

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Location:
Austin, TX
Industry:
Computer Hardware
Work:
Real Intent
Principal Architect
Ibm Jul 2001 - Jan 2017
Research and Development of Formal Verification Tools and Methodologies
Education:
The University of Texas at Austin 2005 - 2008
Doctorates, Doctor of Philosophy, Computer Engineering Indian Institute of Technology, Kharagpur 1995 - 1999
Bachelors, Bachelor of Technology, Electrical Engineering
Skills:
Debugging
C
Perl
Algorithms
Software Development
Unix
Verilog
Computer Architecture
Formal Verification
Cloud Computing
Asic
Solution Architecture
Linux
Software Engineering
Shell Scripting
Embedded Systems
Tcl
Distributed Systems
Languages:
English
Hindi
Hari Mony Photo 2

Hari Mony

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Location:
Austin und Umgebung, Texas
Industry:
Computer-Hardware

Publications

Us Patents

Use Of Time Step Information In A Design Verification System

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US Patent:
6993734, Jan 31, 2006
Filed:
Feb 20, 2003
Appl. No.:
10/371002
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Mark Allen Williams - Plesant Valley NY, US
Assignee:
International Business Machines Corporatioin - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 4, 716 6, 703 13, 703 19
Abstract:
The disclosed design verification system includes a verification engine to model the operation of an integrated circuit and to assess the model's adherence to a property during N time steps of its operation. The value of N is recorded and propagated. The propagated value of N is used to reduce resources expended during subsequent analysis of the integrated circuit by ignoring the model's adherence to the property during the early stages of subsequent analysis (during time steps less than N). The system may include a diameter estimator that identifies a value of N beyond which subsequent modeling of the integrated circuit produces no new states. Property checking is ignored during states having a time step value greater than the estimated diameter.

Incremental, Assertion-Based Design Verification

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US Patent:
7093218, Aug 15, 2006
Filed:
Feb 19, 2004
Appl. No.:
10/782673
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Robert Lowell Kanzelman - Rochester MN, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 19/00
US Classification:
716 5, 716 7, 716 2, 716 3, 703 16
Abstract:
A design verification system includes a first verification engine to model the operation of a first design of an integrated circuit to obtain verification results including the model's adherence to a property during N time steps of its operation, proofs that one or more verification targets can be reached, and verification coverage results for targets that are not reached. A correspondence engine determines the functional correspondence between the first design and a second design of the integrated circuit. Functional correspondence, if demonstrated, enables reuse of the first engine's verification results to reduce resources expended during subsequent analysis of the second design. The correspondence determination may be simplified using a composite model of the integrated circuit having “implies” logic in lieu of “EXOR” logic. The implies logic indicates conditions in which a node in the second design achieves a state that is contrary to the verification results for the first design.

Method For Retiming In The Presence Of Verification Constraints

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US Patent:
7203915, Apr 10, 2007
Filed:
Mar 10, 2005
Appl. No.:
11/077331
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Jiazhao Xu - Mount Kisco NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 1, 716 6, 716 18
Abstract:
A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.

Exploiting Suspected Redundancy For Enhanced Design Verification

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US Patent:
7260799, Aug 21, 2007
Filed:
Feb 10, 2005
Appl. No.:
11/054904
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Robert Lowell Kanzelman - Rochester MN, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 703 14, 703 15
Abstract:
A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate and a candidate gate. A speculatively reduced netlist is generated by replacing the representative gate as the source gate for edges sourced by a candidate gate in the original design. The speculatively reduced netlist is then used either to verify formally the equivalence of the gates by applying a plurality of transformation engines to the speculatively reduced netlist or to perform incomplete search and, if none of the equivalence gates is asserted during the incomplete search, any verification results derived from the incomplete search can be applied to the original model.

System And Method For Engine-Controlled Case Splitting Within Multiple-Engine Based Verification Framework

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US Patent:
7266795, Sep 4, 2007
Filed:
Mar 17, 2005
Appl. No.:
11/082699
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Robert Lowell Kanzelman - Rochester MN, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 716 17
Abstract:
A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of verification engines divides the verification problem into a set of partitions and passes at least one of the set of partitions to a second set of verification engines. Each one of the set of partitions may be passed to a distinctly separate verification engine. A system framework is configured to communicate with an application program and further configured to instantiate at least one verification engine in a user-defined sequence. Included within at least one of the first set of verification engines is a means for communicating verification information to the second set of verification engines.

Method For Preserving Constraints During Sequential Reparameterization

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US Patent:
7299432, Nov 20, 2007
Filed:
Apr 14, 2005
Appl. No.:
11/105611
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Geert Janssen - Putnam Valley NY, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 1, 716 18, 703 14
Abstract:
A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut gates, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is constrained to force one or more constraint gates representing the one or more constraints to evaluate to a forced valuation, and one or more dead-end states of the constraints are identified. The inverse of the dead-end states is applied as don't cares to simplify the relation and the simplified relation is synthesized to form a first gate set. An abstracted design is from the first gate set and verification is performed on the abstracted design to generate verification results.

Method And System For Performing Heuristic Constraint Simplification

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US Patent:
7315996, Jan 1, 2008
Filed:
Sep 22, 2005
Appl. No.:
11/232764
Inventors:
Jason R. Baumgartner - Austin TX, US
Robert L. Kanzelman - Rochester MN, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 5, 716 3, 716 4
Abstract:
A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

Method For Verification Using Reachability Overapproximation

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US Patent:
7322017, Jan 22, 2008
Filed:
Dec 14, 2004
Appl. No.:
11/011245
Inventors:
Jason Raymond Baumgartner - Austin TX, US
Hari Mony - Austin TX, US
Viresh Paruthi - Austin TX, US
Jiazhao Xu - Mount Kisco NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 4, 716 18
Abstract:
A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
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Hari Mony from Cedar Park, TX, age ~46 Get Report