Toshiaki Yoshino - Fremont CA
King Pang - Mountain View CA
LSI Logic Corporation - Milpitas CA
A circuit for calculating a sum of absolute errors for use in full block search matching in a motion estimation processor is disclosed herein, the circuit being easily implemented and capable of running at 54 Mhz. The circuit accesses search window and reference data from memory and loads the data into rows of laterally interacting processing elements having an architecture capable of fast data processing. A sum of absolute errors between all elements of each row of search data and all elements of each row of reference data is calculated, and the absolute error for all rows of processing elements is totalled. From this total sum of absolute error, the motion vector may be predicted for the next frame.